The invention relates to circuitry for and a method of controlling an instruction buffer memory in a data-processing system, whereby instructions are loaded in sequence, subject to controls obtained from a loading indicator that is always increased by no more than a prescribed difference in relation to an instruction address that is constantly to be increased in accordance with one program runthrough and ahead of the instruction address, from a main memory into the instruction buffer memory, from which the instructions, which are always subsequently addressed by the instruction address, are supplied to an instruction decoder for execution.
The article "Maximized Performance by Choosing Best Memory" in Computer Design, Aug. 1, 1987, pp. 89 ff., provides a survey of all the known cache memory systems and the methods of controlling them. Transferring sequences of program instructions that are ready to be executed from a main memory cache by cache into a buffer memory with a more rapid access time and hence to an instruction decoder in a program-controlled data-processing system with a program that is stored in a main memory along with input and output data from a processor is known. The instruction address of an instruction that is ready for execution is always compared with the address range of any instructions in the buffer memory and, if the instruction that is to be addressed is not in the buffer memory, the instruction that is being searched for is loaded along with an associated sequence of instructions that is as long as one cache out of the main memory and into a cache in the buffer memory. The instruction is then loaded therein, addressed there, and supplied to the instruction decoder, and arrives for execution. Further instructions are then selected once a subsequent instruction address has been obtained by program-dependent modification of the state of an instruction counter. The drawback to this circuitry is that the instruction sequences are transferred cache by cache, necessitating a particular transmission time that often results in waiting times that are consumed in transferring instructions that in certain runs are often unneeded and that are located on the cache upstream of the instruction being sought or downstream of a branch in the program at an instruction outside the cache. Furthermore, access on the part of requisite data to the main memory is often impeded during the transfer of such sometimes unneeded instructions.
Decreasing the mean waiting time for access to an instruction by transferring ahead of time a specific number of instructions stored downstream of the instruction that is to be executed to an access instruction buffer memory, from which they are subsequently called up for instruction decoding is also known from Computer Design 21 (1982), 4, p. 64. When, however, the program branches, there will still be a waiting time due to renewed access to the main memory, which will be stressed by the further preliminary unloading, which impedes requisite parallel data access. This is especially a serious drawback when programs are being multiply or cyclically run in loops, whereby the instructions must be obtained again and again from the main memory accompanied by corresponding detriment to the access because a delay in loading always occurs during a program when there is branching at the beginning of the loop due to interception of the first instructions in the program section.